1. Field of the Invention
This invention relates to a defect probability calculating method and a semiconductor device manufacturing method.
2. Description of the Related Art
With miniaturization of semiconductor devices, it becomes more difficult to form desired circuit patterns faithful to a design pattern on a semiconductor wafer. Therefore, various proposals for forming desired circuit patterns are made (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2006-53248).
However, conventionally, patterns in which defects occur with high possibility can be specified, but a quantitative and effective evaluation for defect probability is not made. Therefore, all of the patterns in which defects occur with high possibility must be corrected and it is difficult to efficiently correct the design pattern. Further, it is difficult to make a quantitative and effective evaluation for the manufacturing yield.